Z80180 Datasheet, PDF (69/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
54
Bit
Position Bit/Field
R/W Value Description
2
LNIO
R/W 0 Standard Drive
1 33% Drive on certain external I/O
1
LNCPUCTL R/W 0 Standard Drive
1 33% Drive on CPU control signals
0
LNAD/
R/W 0 Standard Drive
DATA
1 33% drive on A10–A0, D7–D0
Memory Management Unit (MMU)
The Z8X180 features an on-chip MMU which performs the translation of
the CPU 64KB (16-bit addresses 0000H to FFFFH) logical memory
address space into a 1024KB (20-bit addresses 00000H to FFFFFH)
physical memory address space. Address translation occurs internally in
parallel with other CPU operation.
Logical Address Spaces
The 64KB CPU logical address space is interpreted by the MMU as
consisting of up to three separate logical address areas, Common Area 0,
Bank Area, and Common Area 1.
As depicted in Figure 23, a variety of logical memory configurations are
possible. The boundaries between the Common and Bank Areas can be
programmed with 4KB resolution.
UM005001-ZMP0400