Z80180 Datasheet, PDF (171/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
156
CKS
RXS
LSB
MSB
11.5φ
11.5φ
11.5φ
11.5φ
16.5φ
16.5φ
16.5φ
16.5φ
Sampling
RE
EF
Read or write of CSI/O
Transmit/Receive
Data Register
Figure 62. CSI/O Receive Timing–External Clock
Programmable Reload Timer (PRT)
The Z8X180 contains a two channel 16-bit Programmable Reload Timer.
Each PRT channel contains a 16-bit down counter and a 16-bit reload
register. The down counter is directly read and written and a down counter
overflow interrupt can be programmably enabled or disabled. Also, PRT
channel 1 features a TOUT output pin (multiplexed with A18) which can be
set High, Low, or toggled. Thus, PRT1 can perform programmable output
waveform generation.
PRT Block Diagram
The PRT block diagram is depicted in Figure 63. The two channels
feature separate timer data and reload registers and a common status/
UM005001-ZMP0400