Z80180 Datasheet, PDF (66/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
51
Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) (Continued)
Address
Register
Mnemonic Binary
Hex
INT IL Register (Interrupt Vector Low
IL
Register)
XX110011 33H
INT/TRAP Control Register
ITC
XX110100 34H
Reserved
XX110101 35H
Refresh Refresh Control Register
RCR
XX110110 36H
Reserved
MMU MMU Common Base Register
CBR
XX110111 37H
XX111000 38H
MMU Bank Base Register
BBR
XX111001 39H
MMU Common/Bank Area Register CBAR
XX111010 3AH
I/O Reserved
XX111011 3BH
Page
67
68
88
61
62
60
Operation Mode Control Register
I/O Control Register
OMCR
ICR
XX111101 3DH
XX111110 3EH 15
XX111111 3FH 42
UM005001-ZMP0400