Z80180 Datasheet, PDF (172/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
157
control register. The PRT input clock for both channels is equal to the
system clock divided by 20.
Internal Address/Data Bus
Phi ÷ 20
Phi ÷ 20
Timer Data _{Timer Data}
Register 0L _{Register 0H}
: TMDR0L (8) _{: TMDR0H (8)}
Timer Reload Timer Reload
Register 0L Register 0H
: RLDR0L (8) : RLDR0H (8)
Timer Control
Register
: TCR (8)
Timer Data _{Timer Data}
Register 1L _{Register 1H}
: TMDR1L (8) _{: TMDR1H (8)}
TOUT
Timer Reload Timer Reload
Register 1L Register 1H
: RLDR1L (8) : RLDR1H (8)
Interrupt Register
Figure 63. PRT Block Diagram
PRT Register Description
Timer Data Register (TMDR: I/O Address - CH0: 0CH, 0DH; CH1: 15H,
14H). PRT0 and PRT1 each contain 16-bit timer Data Registers (TMDR).
TMDR0 and TMDR1 are each accessed as low and high byte registers
(TMDR0H, TMDR0L and TMDR1H, TMDR1L). During RESET,
TMDR0 and TMDR1 are set to FFFFH.
TMDR is decremented once every twenty clocks. When TMDR counts
down to 0, it is automatically reloaded with the value contained in the
Reload Register (RLDR).
TMDR is read and written by software using the following procedures.
The read procedure uses a PRT internal temporary storage register to
UM005001-ZMP0400