Z80180 Datasheet, PDF (318/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z8018x Family
MPU User Manual
302
Table 57. Internal I/O Registers (Continued)
Register
Mnemonics Address
Remarks
Interrupt Vector Low
IL
Register
INT/TRAP Control
ITC
Register
Refresh Control Register: RCR
33
IL7
IL6
IL5
—
—
—
—
—
bit
during RESET
0
0
0
0
0
0
0
0
R/W
R/W R/W R/W
Interrupt Vector Low
34
bit
TRAP UF0
—
—
—
ITE2 ITE1 ITE0
during RESET
0
0
1
1
1
0
0
0
R/W
R/W
R
R/W R/W R/W
Unidentified Fetch Object
TRAP
INT Enable 2,1,0
36
bit
REFE REFW —
—
—
—
CYC1 CYC0
during RESET
1
1
1
1
1
1
0
0
R/W
R/W
R/W
R/W R/W
Refresh Wait State
Refresh Enable
Interval of Refresh Cycle
00
10 states
01
20
10
40
11
80
Cycle select
UM005001-ZMP0400