Z80180 Datasheet, PDF (141/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
126
Bit
Position Bit/Field R/W
6
RE
R/W
5
TE
R/W
4
RTS0 R/W
3
MPBR/ R/W
EFR
Value Description
Receiver Enable — When RE is set to 1, the ASCI
receiver is enabled. When RE is reset to 0, the receiver is
disabled and any receive operation in progress is
interrupted. However, the RDRF and error flags are not
reset and the previous contents of RDRF and error flags
are held. RE is cleared to 0 in IOSTOP mode, and during
RESET.
Transmitter Enable — When TE is set to 1, the ASCI
transmitter is enabled. When TE is reset to 0, the
transmitter is disabled and any transmit operation in
progress is interrupted. However, the TDRE flag is not
reset and the previous contents of TDRE are held. TE is
cleared to 0 in IOSTOP mode, and during RESET.
Request to Send Channel 0 — When RTS0 is reset to 0,
the RTS0 output pin goes Low. When RTS0 is set to 1,
the RTS0 output immediately goes High.
Multiprocessor Bit Receive/Error Flag Reset — When
multiprocessor mode is enabled (MP in CNTLB is 1),
MPBR, when read, contains the value of the MPB bit for
the last receive operation. When written to 0, the EFR
function is selected to reset all error flags (OVRN, FE and
PE) to 0. MPBR/EFR is undefined during RESET.
UM005001-ZMP0400