Z80180 Datasheet, PDF (317/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z8018x Family
MPU User Manual
301
Table 57. Internal I/O Registers (Continued)
Register
DMA/WAIT Control
Register:
Mnemonics Address
Remarks
DCNTL
32
bit
during RESET
R/W
MWI1 MWI0 IWI1
1
1
1
IWI0 DMS1 DMS0 DIMA1 DIMA0
1
0
0
0
0
R/W R/W R/W R/W R/W
R/W R/W R/W
DMA Ch 1
I/O Memory
Mode Select
DREQi Select, i=1,0
I/O Wait Insertion
Memory Wait Insertion
MWI1,0
00
01
10
11
The number of
wait states
0
1
2
3
IWI1,0
00
01
10
11
The number of
wait states
0
2
3
4
DMSi
1
0
Sense
Edge sense
Level sense
DIM1,0
00
01
10
11
Transfer Mode Address Increment/Decrement
M→ I/O
M→ I/O
I/O→ M
I/O→ M
MAR1+1
MAR1-1
IAR1 fixed
IAR1 fixed
IAR1 fixed
IAR1 fixed
MAR1+1
MAR1-1
UM005001-ZMP0400