Z80180 Datasheet, PDF (310/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z8018x Family
MPU User Manual
294
Table 57. Internal I/O Registers (Continued)
Register
Mnemonics Address
Remarks
ASCI Control Register B CNTLB0
Channel 0:
02
bit
MPBT MP
CTS/
PS
PEO
DR
SS2 SS1
SS0
during RESET
R/W
invalid
R/W
0
R/W
*
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
Divide Ratio
Parity Even or Odd
Clear to send/Prescale
Multi Processor
Multi Processor Bit Transmit
* CTS: Depending on the condition 0f CTS Pin.
PS: Cleared to 0.
Clock Source and
Speed Select
ASCI Control Register B CNTLB1
Channel 1:
0
3
bit
MPBT MP
during RESET invalid
R/W
R/W
0
R/W
CTS/
PS
0
R/W
PEO
0
R/W
DR SS2 SS1
0
R/W
1
R/W
1
R/W
SS0
1
R/W
Divide Ratio
Clock Source and
Speed Select
Parity Even or Odd
Clear to Send/Prescale
Multi Processor
Multi Processor Bit Transmit
General
divide ratio
SS2 1 0
000
001
010
011
100
101
110
111
PS=0
(divide ratio=10)
PS=1
(divide ratio=30)
DR=0 (X 16) DR=1 (X 64) DR=0 (X 16)
φ ÷ 160
÷ 320
÷ 640
÷ 1280
÷ 2560
÷ 5120
÷ 10240
φ ÷ 640
÷ 1280
÷ 2560
÷ 5120
÷ 10240
÷ 20480
÷ 40960
φ ÷ 480
÷ 960
÷ 1920
÷ 3840
÷ 7680
÷ ₁₅₃₆₀
÷ ₃₀₇₂₀
External clock (frequency <φ÷ 40)
DR=1 (X 64)
φ ÷ 1920
÷
3840
÷
7680
÷ 15360
÷ 30720
÷ 61440
÷ 122880
UM005001-ZMP0400