Z80180 Datasheet, PDF (119/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
104
Bits 5–3
Reserved. Must be 0.
Bits 2–0
With DIM1, bit 1 of DCNTL, these bits control which request is
presented to DMA channel 1, as described below:
DIM1 IAR18–16 Request Routed to DMA Channel 1
0
000
DREQ1
0
001
ASCI0 Tx
0
010
ASCI1 Tx
0
011
ext CKA0/DREQ0
0
10X
Reserved
0
1X0
Reserved
0
111
Reserved
1
000
ext DREQ1
1
001
ASCI0 Rx
1
010
ASCI1 Rx
1
011
ext CKA0/DREQ0
1
10X
Reserved
1
1X0
Reserved
1
111
Reserved
DMA Operation
This section discusses the three DMA operation modes for channel 0:
• Memory to/from memory
• Memory to/from I/O
• Memory to/from memory mapped I/O
UM005001-ZMP0400