Z80180 Datasheet, PDF (182/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
167
NMI
Op Code Memory Read/
Acknowledge
Fetch Cycle Write Cycle _{I/O Read Cycle I/O Write Cycle 1st MC}
INT0 Acknowledge
1st MC
T1 T2 T3 T1 T2 T3 T1 T2 Tw T3 T1 T2
Phi
T3 T1 T2 T3 T1 T2 Tw*Tw* T3
E
M1
MREQ
IORQ
NOTE : MC = Machine Cycle
* Two wait states are automatically inserted
Figure 67. E Clock Timing Diagram (During Read/Write Cycle and
Interrupt Acknowledge Cycle
Phi
BUSREQ
BUSACK
E
Last
state
TX TX
BUS RELEASE mode
TX TX
E
E
E
Figure 68. E Clock Timing in BUS RELEASE Mode
UM005001-ZMP0400