Z80180 Datasheet, PDF (280/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z8018x Family
MPU User Manual
264
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Instruction
Machine
Cycle States Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
T1T2T3 1st Op Code 1st Op
Address
Code
010
LD (mn),A
MC2
MC3
T1T2T3 1st operand n
Address
T1T2T3 2nd operand m
Address
010
010
MC4 Ti
*
Z
111
MC5 T1T2T3 mn
A
100
LD A,I
LD A,R ^*4
LD I,A
LD R,A
MC1
MC2
T1T2T3 1st Op Code 1st Op
Address
Code
T1T2T3 2nd Op Code 2nd Op
Address
Code
010
010
LD ww, mn
MC1
MC2
T1T2T3 1st Op Code
Address
T1T2T3 1st operand
Address
1st Op
Code
n
010
010
MC3
T1T2T3 2nd operand m
Address
010
MC1
T1T2T3 1st Op Code 1st Op
Address
Code
010
LD IX,mn
LD IY,mn
MC2
MC3
T1T2T3 2nd Op Code 2nd Op
Address
Code
T1T2T3 1st operand n
Address
010
010
MC4
T1T2T3 2nd operand m
Address
010
*4 In the case of R1 and Z MASK, interrupt request is not sampled.
1
01
0
1
11
1
1
11
1
1
11
1
1
11
1
1
01
0
1
01
1
1
01
0
1
11
1
1
11
1
1
01
0
1
01
1
1
11
1
1
11
1
UM005001-ZMP0400