Z80180 Datasheet, PDF (155/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
140
I/O Instruction
I/O write cycle
Phi
WR
RTS0 Flag
T1
T2
T3
T1
RTS0 Pin
Figure 54. RTS0 Timing Diagram
Figure 55 illustrates the ASCI interrupt request generation circuit.
IEF1
DCD0
RDRF0
OVRN0
PE0
FE0
RIE0
TDRE0
TIE0
ASCI0 Interrupt
Request
RDRF1
OVRN1
PE1
FE1
RIE1
TDRE1
TIE1
Figure 55. ASCI Interrupt Request Circuit Diagram
ASCI1 Interrupt
Request
UM005001-ZMP0400