Z80180 Datasheet, PDF (63/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
48
Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only)
Address
Register
Mnemonic Binary
Hex
ASCI ASCI Control Register A Ch 0
CNTLA0
XX000000 00H
ASCI Control Register A Ch 1
CNTLA1
XX000001 01H
ASCI Control Register B Ch 0
CNTLB0
XX000010 02H
ASCI Control Register B Ch 1
CNTLB1
XX000011 03H
ASCI Status Register Ch 0
STAT0
XX000100 04H
ASCI Status Register Ch 1
STAT1
XX000101 05H
ASCI Transmit Data Register Ch 0 TDR0
XX000110 06H
ASCI Transmit Data Register Ch 1 TDR1
XX000111 07H
ASCI Receive Data Register Ch 0
RDR0
XX001000 08H
ASCI Receive Data Register Ch 1
RDR1
XX001001 09H
ASCI0 Extension Control Register 0 ASEXT0
XX010010 12H
ASCI1 Extension Control Register 1 ASEXT1
XX010011 13H
ASCI0 Time Constant Low
ASTC0L
XX011010 1AH
ASCI0 Time Constant High
ASTC0H
XX001011 1BH
ASCI1 Time Constant Low
ASCT1L
XX001100 1CH
ASCI1 Time Constant High
ASCT1H
XX001101 1DH
CSI0 CSI0 Control Register
CNTR
XX001010 0AH
CSI0 Transmit/Receive Data Register TRD
XX1011 0BH
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UM005001-ZMP0400