Z80180 Datasheet, PDF (117/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
102
Table 15. Channel 1 Transfer Mode
DIM1 DIM0 Transfer Mode
0
0
Memory to I/O
0
1
Memory to I/O
1
0
I/O to Memory
1
1
I/O to Memory
Address Increment/Decrement
MARI +1, IAR1 fixed
MARI -1, IAR1 fixed
IAR1 fixed, MAR1+1
IAR1 fixed, MAR1-1
DMA I/O Address Register Ch. 1 (IAR1B: 2DH) (Z8S180/L180-Class Processor Only)
Bit
7
6
5
4
3
2
Bit/Field
Reserved
R/W
R/W R/W
R/W
R/W
Reset
0
0
0
0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
1
0
R/W
0
Bit
Position Bit/Field R/W Value Description
7
R/W
Alternating Channels
0 DMA Channels are independent
1 Toggle between DMA channels for same device
6
R/W
Currently selected DMA channel when Bit 7 = 1
5–4
Reserved R/W 0 Reserved. Must be 0.
3
R/W 0 TOUT/DREQ is DREQ In
1 TOUT/DREQ is TOUT Out
UM005001-ZMP0400