Z80180 Datasheet, PDF (80/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
65
Packages not containing an A19 pin or situations using TOUT
Note: _{instead of A18 yield an address capable of only addressing 512K}
of physical space.
Interrupts
The Z8X180 CPU has twelve interrupt sources, 4 external and 8 internal,
with fixed priority. (Reference Figure 31.)
This section explains the CPU registers associated with interrupt
processing, the TRAP interrupt, interrupt response modes, and the
external interrupts. The detailed discussion of internal interrupt
generation (except TRAP) is presented in the appropriate hardware
section (that is, PRT, DMAC, ASCI, and CSI/O).
Higher (1)
Priority (2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
Lower ⁽¹¹⁾
Priority (12)
TRAP (Undefined Op Code Trap)
NMI (Non Maskable Interrupt)
INT0 (Maskable Interrupt Level 0)
INT1 (Maskable Interrupt Level 1)
INT2 (Maskable Interrupt Level 2)
Timer 0
Timer 1
DMA channel 0
DMA channel 1
Clocked Serial I/O Port
Asynchronous SCI channel 0
Asynchronous SCI channel 1
Internal Interrupt
External Interrupt
Internal Interrupt
Figure 31. Interrupt Sources
Interrupt Control Registers and Flags. The Z8X180 has three registers and
two flags which are associated with interrupt processing.
UM005001-ZMP0400