Z80180 Datasheet, PDF (95/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
80
Last MC
Phi
INT0
A0–A19
M1
Vector Lower
Address Read
INT0 Acknowledge Cycle
PC is pushed onto stack
Interrupt
Manipulation
Cycle
T1 T2 _{TW* TW*} T3 Ti T1 _T2 T3 T1 T2 T3 T1 T2 T3 T1 T2
Op Code
Fetch Cycle
T1 T2 T3
Starting address
PC
SP-1
SP-2
Vector
Vector+1
MREQ
IORQ
RD
WR
D0–D7
ST
Lower Vector
PCH
Starting Address
(Lower Address)
PCL
Starting Address
(Upper Address)
*Two Wait States are automatically inserted
Figure 40. INT0 Interrupt Mode 2 Timing Diagram
INT1, INT2
The operation of external interrupts INT1 and INT2 is a vector mode
similar to INT0 Mode 2. The difference is that INT1 and INT2 generate
the low-order byte of vector table address using the IL (Interrupt Vector
Low) register rather than fetching it from the data bus. This difference is
UM005001-ZMP0400