Z80180 Datasheet, PDF (158/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
143
Table 19. ASCI Baud Rate Selection (Continued)
Sampling
Prescaler
Rate
Baud Rate
Divide
SS2 SS1 SS0 Divide
PS Ratio DR Rate
Ratio
General
Divide
Ratio
Baud Rate (Example)
(BPS)
φ= 6.144 φ= 4.608 φ= 3.072
MHz
MHz MHz
CKA
Clock
I/O Frequency
000
÷ 1 φ÷ 480
9600
φ÷ 30
001
2
960
4800
60
010
4
1920
2400
120
0 16 ^{0 1 1}
100
8
3840
16
7680
1200
600
0 240
480
101
32 15360
300
960
1 φ÷ 30
110
111
000
64 30720
— fc ÷ 16
÷ 1 φ÷ 1920
150
—
—
2400
1920
— I fc
φ÷ 30
001
2
3840
1200
60
010
4
7680
600
120
1 64 ^{0 1 1}
100
8 15360
16 30720
300
0 240
150
480
101
32 61440
75
960
110
111
64 122880
— fc ÷ 64
37.5
—
—
1920
— I fc
Baud Rate Generator
(Z8S180/Z8L180-Class Processors Only)
The Z8S180/Z8L180 Baud Rate Generator (BRG) features two modes.
The first is the same as in the Z80180. The second is a 16-bit down
counter that divides the processor clock by the value in a 16-bit time
constant register, and is identical to the DMSCC BRG. This feature
UM005001-ZMP0400