Z80180 Datasheet, PDF (214/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z8018x Family
MPU User Manual
198
Memory Read/Write Cycle timing is the sam as I/O Read/Write Cycle
except there are no automatica Wait States (TW), and MREQ is active
instead of IORQ.
PH I
31
32
INT0,1,2
33
NMI
M1
IO RQ
Data IN
M REQ
RFSH
34
BUSREQ
BUSACK
A19 –0, D7–0
MREQ, RD
W R, IORQ
H ALT
10
30
28
14
15
29
16
39
41
40
42
35
34
35
36
37
38
38
OutputBuffe r Off
43
44
Figure 82. AC Timing Diagram 2
UM005001-ZMP0400