Z80180 Datasheet, PDF (37/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
22
T1
Phi
A0–A19
D0–D7
WAIT
MREQ
RD
WR
Read Cycle
T2
TW
T3
T1
Read data
Write Cycle
T2
TW
T3
Write data
Figure 12. Memory Read/Write (with Wait State) Timing Diagram
I/O Read/Write Timing
I/O Read/Write operations differ from memory Read/Write operations in
the following three ways:
• The IORQ (I/O Request) signal is asserted Low instead of the MREQ
signal
• The 16-bit I/O address is not translated by the MMU
• A16–A19 are held Low
At least one Wait State (TW) is always inserted for I/O read and write
cycles (except internal I/O cycles).
Figure 13 illustrates I/O read/write timing with the automatically inserted
Wait State (TW).
UM005001-ZMP0400