Z80180 Datasheet, PDF (272/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z8018x Family
MPU User Manual
256
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Instruction
Machine
Cycle States Address
Data
RD WR MREQ IORQ M1 HALT ST
DJNZ j
(If Br ≠ 0)
MC1
MC2
MC3
T1T2T3 1st Op Code
Address
Ti*2 *
T1T2T3 1st operand
Address
1st Op
Code
Z
j-2
010
111
010
1
01
0
1
11
1
1
11
1
MC4~M TiTi *
C5
Z
111
1
11
1
DJNZ j
(If Br=0)
MC1
MC2
MC3
T1T2T3 1st Op Code
Address
Ti*1 *
T1T2T3 1st operand
Address
1st Op
Code
Z
j-2
010
111
010
1
01
0
1
11
1
1
11
1
EI*3
MC1
T1T2T3 1st Op Code 1st Op
010
1
01
0
Address
Code
EX DE, HL
EXX
MC1
T1T2T3 1st Op Code 1st Op
Address
Code
010
1
01
0
EX AF, AF’
MC1
T1T2T3 1st Op Code 1st
010
Address
Op Code
1
01
0
MC2 Ti
*
Z
111
1
11
1
MC1
T1T2T3 1st Op Code 1st Op
Address
Code
010
1
01
0
EX (SP), HL
MC2
MC3
T1T2T3 SP
T1T2T3 SP+1
DATA
DATA
010
010
1
11
1
1
11
1
MC4 Ti
*
Z
111
1
11
1
MC5 T1T2T3 SP+1
H
100
1
11
1
MC6 T1T2T3 SP
L
100
1
11
1
*2 DMA,REFRESH, or BUS RELEASE cannot be executed after this state. (Request is ignored)
*3 Interrupt request is not sampled.
UM005001-ZMP0400