Z80180 Datasheet, PDF (42/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
27
CPU Internal Operation
Bus Release Cycle CPU Cycle
T1 T1 T1 T1 TX TX TX T1
Phi
A0–A19
D0–D7
MREQ
IORQ
RD, WR
BUSREQ
BUSACK
Figure 17. Bus Exchange Timing During CPU Internal Operation
Wait State Generator
To ease interfacing with slow memory and I/O devices, the Z8X180 uses
Wait States (TW) to extend bus cycle timing. A Wait State(s) is inserted
based on the combined (logical OR) state of the external WAIT input and
an internal programmable wait state (TW) generator. Wait States (TW)
can be inserted in both CPU execution and DMA transfer cycles.
When the external WAIT input is asserted Low, Wait State(s) (TW) are
inserted between T2 and T3 to extend the bus cycle duration. The WAIT
input is sampled at the falling edge of the system clock in T2 or TW. If
the WAIT input is asserted Low at the falling edge of the system clock in
TW, another TW is inserted into the bus cycle.
Note: WAIT input transitions must meet specified setup and hold
times. This specification can easily be accomplished by
UM005001-ZMP0400