Z80180 Datasheet, PDF (103/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
88
Refresh Control Register (RCR)
The RCR specifies the interval and length of refresh cycles, while
enabling or disabling the refresh function.
Refresh Control Register (RCR: 36H)
Bit
7
6
5
4
3
Bit/Field REFE REFW
?
R/W
R/W R/W
?
Reset
1
1
?
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
2
1
0
CYC1 CYC0
R/W R/W
0
0
Bit
Position Bit/Field R/W
7
REFE R/W
6
REFW R/W
1–0
CYC1–0 R/W
Value Description
REFE: Refresh Enable
0 Disables the refresh controller
1 Enables refresh cycle insertion.
Refresh Wait (bit 6)
0 Causes the refresh cycle to be two clocks in duration.
1 Causes the refresh cycle to be three clocks in duration by
adding a refresh wait cycle (TRW).
Cycle Interval — CYC1 and CYC0 specify the interval
(in clock cycles) between refresh cycles. In the case of
dynamic RAMs requiring 128 refresh cycles every 2 ms
(or 256 cycles in every 4 ms), the required refresh interval
is less than or equal to 15.625 µs. Thus, the underlined
values indicate the best refresh interval depending on
CPU clock frequency. CYC0 and CYC1 are cleared to 0
during RESET. Refer to Table 11.
UM005001-ZMP0400