Z80180 Datasheet, PDF (114/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
99
Table 13. Channel 0 Source
SM1
0
0
1
1
SM0
0
1
0
1
Memory/I/O
Memory
Memory
Memory
I/O
Address lncrement/Decrement
+1
-1
fixed
fixed
Table 14 describes all DMA TRANSFER mode combinations of DM0
DM1, SM0 SM1. Because I/O to/from I/O transfers are not implemented,
12 combinations are available.
Table 14. Transfer Mode Combinations
DM1 DM0 SM1 SM0 Transfer Mode
0 0 0 0 Memory to Memory
0 0 0 1 Memory to Memory
0 0 1 0 Memory* to Memory
0 0 1 1 I/O to Memory
0 1 0 0 Memory to Memory
0 1 0 1 Memory to Memory
0 1 1 0 Memory to Memory
0 1 1 1 I/O to Memory
1 0 0 0 Memory to Memory*
1 0 0 1 Memory to Memory*
1 0 1 0 Reserved
1 0 1 1 Reserved
Increment/Decrement
SAR0+1, DAR0+1
SAR0-1, DAR0+1
SAR0 fixed, DAR0+ 1
SAR0 fixed DAR0+1
SAR0+1, DAR0-1
SAR0-1,DAR0-1
SAR0 fixed, DAR0-1
SAR0 fixed. DAR0-1
SAR0+ 1, DAR0 fixed
SAR0-1, DAR0 fixed
UM005001-ZMP0400