Z80180 Datasheet, PDF (106/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
91
• DREQ Input
Level- and edge-sense DREQ input detection are selectable.
TEND Output Used to indicate DMA completion to external devices.
• Transfer Rate
Each byte transfer occurs every 6 clock cycles. Wait States can be
inserted in DMA cycles for slow memory or I/O devices. At the
system clock (φ) = 6 MHz, the DMA transfer rate is as high as 1.0
megabytes/second (no Wait States).
There is an additional feature disc for DMA interrupt request by DMA
END. Each channel has the following additional specific capabilities:
Channel 0
• Memory to memory
• Memory to I/O
• Memory to memory mapped I/O transfers.
• Memory address increment, decrement, no-change
• Burst or cycle steal memory to/from memory transfers
• DMA to/from both ASCI channels
• Higher priority than DMAC channel 1
Channel 1
• Memory to/from I/O transfer
• Memory address increment, decrement
DMAC Registers
Each channel of the DMAC (channel 0, 1) contains three registers
specifically associated with that channel.
UM005001-ZMP0400