Z80180 Datasheet, PDF (150/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
135
ASCI0 Extension Control Register (I/O Address: 12H) (Z8S180/L180-Class Processors
Only)
Bit
7
6
5
4
3
Bit/Field
RDRF
Int
Inhibit
DCD0
Disable
CTS0
Disable
X1 Bit
Clk
ASCI0
BRG0
Mode
R/W
R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
2
Break
Feature
Enable
R/W
0
1
Break
Detect
(RO)
R/W
0
0
Send
Break
R/W
0
Bit
Position Bit/Field R/W Value Description
7
RDRF R/W 0 RDRF Interrupt Inhibit On
Interrupt
1 RDRF Interrupt Inhibit Off
Inhibit
6
DCD0 R/W 0 DCD0 Auto-enables Rx
Disable
1 DCD0 advisory to SW
5
CTS0
R/W 0 CTS0 Auto-enable Tx
Disable
1 CTS0 advisory to SW
4
X1 Bit R/W 0 CKA0 /16 or /64
Clk
1 CKA0 is bit clock
ASCI0
3
BRG0
R/W 0 As S180
Mode
1 Enable 16-bit BRG counter
2
Break
R/W 0 Break Feature Enable On
Feature
1 Break Feature Enable Off
Enable
1
Break
R/W 0 Break Detect On
Detect
1 Break Detect Off
(RO)
UM005001-ZMP0400