Z80180 Datasheet, PDF (186/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
171
Crystal
20 mm max
GND
Signal line layout must
avoid shaded areas
C_L
C_L
1
2
64
Phi
3
Z8X180
Top View
Note: Pin mumbers valid only
for DIP configuration
Figure 73. Example of Board Design
Circuit Board design should observe the following parameters.
• Locate the crystal and load capacitors as close to the IC as physically
possible to reduce noise.
• Signal lines must not run parallel to the clock oscillator inputs. In
particular, the clock input circuitry and the system clock output (pin 64)
must be separated as much as possible.
• V_CC power lines must be separated from the clock oscillator input
circuitry.
• Resistivity between XTAL or EXTAL and the other pins must be
greater than 10M ohms.
Signal line layout must avoid areas marked with the shaded area of Figure
73.
UM005001-ZMP0400