Z80180 Datasheet, PDF (102/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
87
Refresh cycles may be programmed to be either two or three clock cycles
in duration by programming the REFW (Refresh Wait) bit in the Refresh
Control Register (RCR). The external WAIT input and the internal Wait
State generator are not effective during refresh.
Figure 44 depicts the timing of a refresh cycle with a refresh wait (TRW)
cycle.
MCi
Refresh cycle MCi+1
TR1 TRW* TR2
Refresh signal
(Internal signal)
Refresh address
A0 — A7
MREQ
RFSH
NOTE: * If three refresh cycles are specified, TRW is inserted.
Otherwise, TRW is not inserted
MC: Machine Cycle
Figure 44. Refresh Cycle Timing Diagram
UM005001-ZMP0400