Z80180 Datasheet, PDF (47/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
32
• The HALT output pin is asserted Low
• The external bus activity consists of repeated dummy fetches of the
Op Code following the HALT instruction.
Essentially, the Z80180 operates normally in HALT mode, except that
instruction execution is stopped.
HALT mode can be exited in the following two ways:
• RESET Exit from HALT Mode
If the RESET input is asserted Low for at least six clock cycles,
HALT mode is exited and the normal RESET sequence (restart at
address 00000H) is initiated.
• Interrupt Exit from HALT mode
When an internal or external interrupt is generated, HALT mode is
exited and the normal interrupt response sequence is initiated.
If the interrupt source is masked (individually by enable bit, or globally
by IEF1 state), the Z80180 remains in HALT mode. However, NMI
interrupt initiates the normal NMI interrupt response sequence
independent of the state of IEF1.
HALT timing is illustrated in Figure 20.
UM005001-ZMP0400