Z80180 Datasheet, PDF (314/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z8018x Family
MPU User Manual
298
Table 57. Internal I/O Registers (Continued)
Register
Mnemonics Address
Remarks
Timer Data Register
TMDR1L
Channel 1L:
Timer Data Register
TMDR1H
Channel 1H:
Timer Reload Register RLDR1L
Channel 1L
Timer Reload Register RLDR1H
Channel 1H:
Free Running Counter: FRC
DMA Source Address SAR0L
Register Channel 0L:
DMA Source Address SAR0H
Register Channel 0H:
DMA Source Address SAR0B
Register Channel 0B:
DMA Destination Address DAR0L
Register Channel 0L:
DMA Destination Address DAR0H
Register Channel 0H:
DMA Destination Address DAR0B
Register Channel 0B:
DMA Byte Count Register BCROL
Channel 0L:
DMA Byte Count Register BCROH
Channel 0H:
DMA Memory Address MAR1L
Register
Channel 1L:
DMA Memory Address MAR1H
Register
Channel 1H:
14
15
16
17
18
20
21
22
23
24
25
26
27
28
Read only
Bits 0-2 (3) are used for SAR0B
A₁₉*, A₁₈, A₁₇, A₁₆
XX
00
XX
01
XX
10
XX
11
Bits 0-2 (3) are used for DAR0B
A₁₉*, A₁₈, A₁₇, A₁₆
XX
00
XX
01
XX
10
XX
11
29
DMA Transfer Request
DREQ₀ (external)
RDR0 (ASCI0)
RDR1 (ASCI1)
Not used
DMA Transfer Request
DREQ₀ (external)
TDR0 (ASCI0)
TDR1 (ASCI1)
Not used
UM005001-ZMP0400
* In the R1 and Z mask, these DMAC registers are expanded from 4 bits to 3 bits in the
package version of CP-68.