Z80180 Datasheet, PDF (40/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
25
The external bus is IDLE while the CPU computes the effective address.
Finally, the computed memory location is written with the contents of the
CPU register (g).
RESET Timing
Figure 15 depicts the Z8X180 hardware RESET timing. If the RESET pin
is Low for six or more clock cycles, processing is terminated and the
Z8X180 restarts execution from (logical and physical) address 00000H.
Phi
RESET
RESET
6 or more clocks
RESET Start
Op Code Fetch Cycle
T1 T2
A0–A19
High impedance _{Restart address (00000H)}
Figure 15. RESET Timing Diagram
BUSREQ/BUSACK Bus Exchange Timing
The Z8X180 can coordinate the exchange of control, address and data bus
ownership with another bus master. The alternate bus master can request
the bus release by asserting the BUSREQ (Bus Request) input Low. After
the Z8X180 releases the bus, it relinquishes control to the alternate bus
master by asserting the BUSACK (Bus Acknowledge) output Low.
The bus may be released by the Z8X180 at the end of each machine cycle.
In this context, a machine cycle consists of a minimum of three clock
cycles (more if wait states are inserted) for Op Code fetch, memory read/
write, and I/O read/write cycles. Except for these cases, a machine cycle
corresponds to one clock cycle.
UM005001-ZMP0400