Z80180 Datasheet, PDF (268/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z8018x Family
MPU User Manual
252
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Instruction
Machine
Cycle States Address
Data
ADD A,g
ADC A,g
SUB g
SBC A,g
AND g
OR g
XOR g
CP g
MC1
MC2
ADD A,m
ADC A,m
SUB m
SBC A,m
AND m
OR m
XOR m
CP m
MC1
MC2
ADD A, (HL)
ADC A, (HL)
SUB (HL)
SBC A, (HL)
AND HU
OR (HL)
XOR (HL)
CP (HL)
MC1
MC2
ADD A, (IX+ d)
ADD A, (IY+d)
ADC A, (IX+d)
ADC A, (IY+d)
SUB (lX+d)
SUB (IY+d)
SBC A, (IX+ d)
MC1
MC2
SBC A, (IY+ d) MC3
AND (IX+d)
T1T2T3 1st Op Code
Address
Ti
*
1st Op
Code
Z
T1T2T3 1st Op Code
Address
T1T2T3 1st operand
Address
1st Op
Code
m
T1T2T3 1st Op Code
Address
T1T2T3 HL
1st Op
Code
DATA
T1T2T3 1st Op Code 1st Op
Address
Code
T1T2T3 2nd Op Code 2nd Op
Address
Code
T1T2T3 1st operand d
Address
RD WR MREQ IORQ M1 HALT ST
010
1
01
0
111
1
11
1
010
010
1
01
0
1
11
1
010
010
1
01
0
1
11
1
010
010
1
01
0
1
01
1
010
1
11
1
UM005001-ZMP0400