Z80180 Datasheet, PDF (107/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
92
Channel 0
• SAR0–Source Address Register
• DAR0–Destination Address Register
• BCR0–Byte Count Register
Channel 1
• MAR1–Memory Address Register
• IAR1–I/O Address Register
• BCR1–Byte Count Register
The two channels share the following three additional registers in common:
• DSTAT–DMA Status Register
• DMODE–DMA Mode Register
• DCNTL–DMA Control Register
DMAC Block Diagram
Figure 45 depicts the Z8X180 DMAC Block Diagram.
UM005001-ZMP0400