Z80180 Datasheet, PDF (209/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z8018x Family
MPU User Manual
194
Table 31. Z8S180 AC Characteristics (Continued) V_DD = 5V ±10% or
V_DD = 3.3V ±10%; 33-MHz Characteristics Apply Only to 5V
Z8S180— 20 Z8S180— 33
MHz
MHz
No. Symbol Item
Min Max Min Max Unit
13
t_RDD2 PHI Fall to RD Rise Delay
—
25 —
15
ns
14
t_M1D2 PHI Rise to M1 Rise Delay
—
40 —
15
ns
15
t_DRS Data Read Set-up Time
10 —
5
—
ns
16
t_DRH Data Read Hold Time
0
—
0
—
ns
17
t_STD1 PHI Fall to ST Fall Delay
—
30 —
15
ns
18
t_STD2 PHI Fall to ST Rise Delay
—
30 —
15
ns
19
t_WS WAIT Set-up Time to PHI Fall
15 —
10 —
ns
20
t_WH WAIT Hold Time from PHI Fall
10
—
5
—
ns
21
t_WDZ PHI Rise to Data Float Delay
—
35 —
20
ns
22
t_WRD1 PHI Rise to WR Fall Delay
—
25 —
15
ns
23
t_WDD PHI Fall to Write Data Delay Time —
25 —
15
ns
24
t_WDS Write Data Set-up Time to WR Fall 10 —
10 —
ns
25
t_WRD2 PHI Fall to WR Rise Delay
—
25 —
15
ns
26
t_WRP WR Pulse Width (Memory Write 80 —
45 —
ns
Cycle)
26a
WR Pulse Width (I/O Write Cycle) 150 —
70 —
ns
27
t_WDH Write Data Hold Time from WR Rise 10 —
5
—
ns
28
t_IOD1 PHI Fall to IORQ Fall Delay IOC —
25 —
15
ns
=1
PHI Rise to IORQ Fall Delay IOC —
25 —
15
=0
29
t_IOD2 PHI Fall to IORQ Rise Delay
30
t_IOD3 M1 Fall to IORQ Fall Delay
31
t_INTS INT Set-up Time to PHI Fall
32
t_INTH INT Hold Time from PHI Fall
—
25 —
15
ns
125 —
80 —
ns
20 —
15 —
ns
10 —
10 —
ns
UM005001-ZMP0400