Z80180 Datasheet, PDF (58/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
43
IOA7 — IOA6 = 1 1
IOA7 — IOA6 = 1 0
IOA7 — IOA6 = 0 1
IOA7 — IOA6 = 0 0
00FFH
00C0H
00BFH
0080H
007FH
0040H
003FH
0000H
Figure 22. I/O Address Relocation
Internal I/O Registers Address Map
The internal I/O register addresses are described in Table 6 and Table 7.
These addresses are relative to the 64-byte boundary base address specified
in ICR.
I/O Addressing Notes
The internal I/O register addresses are located in the I/O address space
from 0000H to 00FFH (16-bit I/O addresses). Thus, to access the internal
I/O registers (using I/O instructions), the high-order 8 bits of the 16-bit
I/O address must be 0.
The conventional I/O instructions (OUT (m), A/IN A, (m) / OUTI/INI,
for example) place the contents of a CPU register on the high-order 8 bits
of the address bus, and thus may be difficult to use for accessing internal
I/O registers.
For efficient internal I/O register access, a number of new instructions
have been added, which force the high-order 8 bits of the 16-bit I/O
UM005001-ZMP0400