Z80180 Datasheet, PDF (94/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
79
The vector table address is located on 256 byte boundaries in the 64KB
logical address space programmed in the 8-bit Interrupt Vector Register
(1). Figure 39 depicts the INT0 Mode 2 Vector acquisition.
16-bit Vector
Memory
Interrupt Vector
Register I
8-bit on
Data Bus
Vector + 1 ^{High-order 8 bits}
of starting address
Vector
Low-order 8 bits
of starting address
Offset
256 Bytes
Vector
Table
Figure 39. INT0 Mode 2 Vector Acquisition
During the INT0 Mode 2 acknowledge cycle, the low-order 8 bits of the
vector is fetched from the data bus at the rising edge of T3 and the CPU
acquires the 16-bit vector.
Next, the PC is stacked. Finally, the 16-bit restart address is fetched from
the vector table and execution begins at that address.
Note: External vector acquisition is indicated by both MI and IORQ
LOW. Two Wait States (TW) are automatically inserted for
external vector fetch cycles.
During RESET the Interrupt Vector Register (I) is initialized to 00H and,
if necessary, should be set to a different value prior to the occurrence of a
Mode 2 INT0 interrupt. Figure illustrates INT0 interrupt Mode 2 Timing.
UM005001-ZMP0400