Z80180 Datasheet, PDF (105/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
90
3. Refresh cycles are suppressed during SLEEP mode. If a refresh cycle
is requested during SLEEP mode, the refresh cycle request is
internally latched (until replaced with the next refresh request). The
latched refresh cycle is inserted at the end of the first machine cycle
after SLEEP mode is exited. After this initial cycle, the time at which
the next refresh cycle occurs depends on the refresh time and has no
timing relationship with the exit from SLEEP mode.
4. Regarding (2) and (3), the refresh address is incremented by one for
each successful refresh cycle, not for each refresh request. Thus,
independent of the number of missed refresh requests, each refresh
bus cycle uses a refresh address incremented by one from that of the
previous refresh bus cycles.
DMA Controller (DMAC)
The Z8X180 contains a two-channel DMA (Direct Memory Access)
controller which supports high speed data transfer. Both channels
(channel 0 and channel 1) feature the following capabilities:
• Memory Address Space
Memory source and destination addresses can be directly specified
anywhere within the 1024KB physical address space using 20-bit
source and destination memory addresses. In addition, memory
transfers can arbitrarily cross 64KB physical address boundaries
without CPU intervention.
• I/O Address Space
I/O source and destination addresses can be directly specified
anywhere within the 64KB I/O address space (16-bit source and
destination I/O addresses).
• Transfer Length
Up to 64KB are transferred based on a 16- bit byte count register.
UM005001-ZMP0400