Z80180 Datasheet, PDF (161/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
146
causes for an ASCI Receive interrupt (PE, FE, OVRN, and for ASCI0,
DCD) continue to request RX interrupt if the RIE bit is 1. The Rx DMA
request is inhibited if PE or FE or OVRN is set, so that software can
detect where an error occurred. When the RIE bit is 0, as it is after a
Reset, RDRF causes an ASCI interrupt if RIE is 1.
Clocked Serial I/O Port (CSI/O)
The Z8X180 includes a simple, high-speed clock, synchronous serial I/O
port. The CSI/O includes transmit/receive (half-duplex), fixed 8-bit data,
and internal or external data clock selection. High-speed operation (baud
rate 200Kbps at fC = 4 MHz) is provided. The CSI/O is ideal for
implementing a multiprocessor communication link between multiple
Z8X180s. These secondary devices may typically perform a portion of the
system I/O processing, (that is, keyboard scan/decode, LDC interface, for
instance).
CSI/O Block Diagram
The CSI/O block diagram is illustrated in Figure 57. The CSI/O consists
of two registers–the Transmit/Receive Data Register (TRDR) and Control
Register (CNTR).
UM005001-ZMP0400