Z80180 Datasheet, PDF (62/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
47
Table 6. I/O Address Map for Z80180-Class Processors Only (Continued)
Address
Register
INT IL Register (Interrupt Vector Low
Register)
INT/TRAP Control Register
Reserved
Refresh Refresh Control Register
Reserved
MMU MMU Common Base Register
MMU Bank Base Register
MMU Common/Bank Area Register
I/O Reserved
Mnemonic Binary
Hex
IL
XX110011 33H
ITC
RCR
CBR
BBR
CBAR
XX110100 34H
XX110101 35H
XX110110 36H
XX110111 37H
XX111000 38H
XX111001 39H
XX111010 3AH
XX111011 3BH
Page
67
68
88
61
62
60
Operation Mode Control Register
I/O Control Register
OMCR
ICR
XX111101 3DH
XX111110 3EH 15
XX111111 3FH 42
UM005001-ZMP0400