Z80180 Datasheet, PDF (110/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
95
DMA Status Register (DSTAT)
DSTAT is used to enable and disable DMA transfer and DMA termination
interrupts. DSTAT also determines DMA transfer status, that is, completed
or in progress.
DMA Status Register (DSTAT: 30H)
Bit
7
6
5
4
3
2
1
0
Bit/Field
DE1 DE0 DWE1 DWE0 DIE1 DIE0
?
DME
R/W
R/W R/W
W
W
R/W R/W
?
R
Reset
0
0
1
1
0
0
?
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W
7
DE1
R/W
Value Description
Enable Channel 1 — When DE1 = 1 and DME = 1,
channel 1 DMA is enabled. When a DMA transfer
terminates (BCR1 = 0), DE1 is reset to 0 by the DMAC.
When DE1 = 0 and the DMA interrupt is enabled (DIE1 =
1), a DMA interrupt request is made to the CPU.
To perform a software write to DE1, DWE1 is written with
0 during the same register write access. Writing DE1 to 0
disables channel 1 DMA, but DMA is restartable. Writing
DE1 to 1 enables channel 1 DMA and automatically sets
DME (DMA Main Enable) to 1. DE1 is cleared to 0 during
RESET.
UM005001-ZMP0400