Z80180 Datasheet, PDF (109/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
94
DMA Destination Address Register Channel 0 (DAR0 I/O Address =
23H to 25H)
Specifies the physical destination address for channel 0 transfers. The
register contains 20 bits and can specify up to 1024KB memory addresses
or up to 64KB I/O addresses. Channel 0 destination can be memory, I/O,
or memory mapped I/O.
DMA Byte Count Register Channel 0 (BCR0 I/O Address = 26H to
27H)
Specifies the number of bytes to be transferred. This register contains 16
bits and may specify up to 64KB transfers. When one byte is transferred,
the register is decremented by one. If n bytes are transferred, n is stored
before the DMA operation.
DMA Memory Address Register Channel 1 (MAR1: I/O Address =
28H to 2AH)
Specifies the physical memory address for channel 1 transfers. This
address may be a destination or source memory address. The register
contains 20 bits and may specify up to 1024KB memory address.
DMA I/O Address Register Channel 1 (IAR1: I/O Address = 2BH to
2CH)
Specifies the I/O address for channel 1 transfers. This address may be a
destination or source I/O address. The register contains 16 bits and may
specify up to 64KB I/O addresses.
DMA Byte Count Register Channel 1 (BCR1: I/O Address = 2EH to
2FH)
Specifies the number of bytes to be transferred. This register contains 16
bits and may specify up to 64KB transfers. When one byte is transferred,
the register is decremented by one.
UM005001-ZMP0400