Z80180 Datasheet, PDF (21/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
6
Phi
Timing
Generator
Bus State Control
CPU
Interrupt
A18/TOUT
16-bit
Programmable
Reload
Timers
TXS
RXS/CTS1
CKS
Clocked
Serial I/O
Port
MMU
DMACs
(2)
DREQ1
TEND1
Asynchronous
SCI
(Channel 0)
TXA0
CKA0/DREQ0
RXA0
RTS0
CTS0
DCD0
Asynchronous
SCI
(channel 0)
TXA1
CKA1/TEND0
RXA1
Address
Data
Buffer
Buffer
V_CC
V_SS
A0–A19
D0–DF
Figure 4. Z80180/Z8S180/Z8L180 Block Diagram
UM005001-ZMP0400