Z80180 Datasheet, PDF (111/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
96
Bit
Position Bit/Field R/W
6
DE0
R/W
5
DWE1 W
4
DWE0 W
3
DIE1 R/W
2
DIE0
Value Description
Enable Channel 0 — When DE0 = 1 and DME = 1,
channel 0 DMA is enabled. When a DMA transfer
terminates BCR0 = 0), DE0: is reset to 0 by the DMAC.
When DE0 = 0 and the DMA interrupt is enabled (DIE0 =
1), a DMA interrupt request is made to the CPU.
To perform a software write to DE0, DWE0 must be written
with 0 during the same register write access. Writing DE0 to
0 disables channel 0 DMA. Writing DE0 to 1 enables
channel 0 DMA and automatically sets DME (DMA Main
Enable) to 1. DE0 is cleared to 0 during RESET.
Bit Write Enable 1 — When performing any software
write to DEI, DWE1 must be written with 0 during the
same access. DWE1 write value of 0 is not held and
DWE1 is always read as 1.
Bit Write Enable 0 — When performing any software
write to DE0, DWE0 must be written with 0 during the
same access. DWE0 write value of 0 is not held and
DWE0 is always read as 1.
DMA Interrupt Enable Channel 1 — When DIE1 is set
to 1, the termination channel 1 DMA transfer (indicated
when DE1 is 0) causes a CPU interrupt request to be
generated. When DIE1 is 0, the channel 1 DMA
termination interrupt is disabled. DIE1 is cleared to 0
during RESET.
DMA Interrupt Enable Channel 0 — When DIE0 is set
to 1, the termination channel 0 of DMA transfer
(indicated when DE0 is 0) causes a CPU interrupt request
to be generated. When DIE0 is 0, the channel 0 DMA
termination interrupt is disabled. DIE0 is cleared to 0
during RESET.
UM005001-ZMP0400