Z80180 Datasheet, PDF (153/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
138
ASCI1 Time Constant Low Register (I/O Address: 1CH) (Z8S180/L180-Class Processors
Only)
Bit
7
6
5
4
3
2
1
0
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
ASCI1 Time Constant High Register (I/O Address: 1DH) (Z8S180/L180-Class Processors
Only)
Bit
7
6
5
4
3
2
1
0
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Modem Control Signals
ASCI channel 0 has CTS0, DCD0 and RTS0 external modem control
signals. ASCI channel 1 has a CTS1 modem control signal which is
multiplexed with Clocked Serial Receive Data (RXS).
CTS0: Clear to Send 0 (Input)
The CTS0 input allows external control (start/stop) of ASCI channel 0
transmit operations. When CTS0 is High, the channel 0 TDRE bit is held
at 0 whether or not the TDR0 (Transmit Data Register) is full or empty.
When CTS0 is Low, TDRE reflects the state of TDR0. The actual
transmit operation is not disabled by CT High, only TDRE is inhibited:
DCD0: Data Carrier Detect 0 (Input)
The DCD0 input allows external control (start/stop) of ASCI channel 0
receive operations. When DCD0 is High, the channel 0 RDRF bit is held
at 0 whether or not the RDR0, (Receive Data Register) is full or empty.
UM005001-ZMP0400