Z80180 Datasheet, PDF (156/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
141
ASCI to/from DMAC Operation
Operation of the ASCI with the on-chip DMAC channel 0 requires that the
DMAC be correctly configured to use the ASCI flags as DMA request signals.
ASCI and RESET
During RESET, the ASCI status and control registers are initialized as
defined in the individual register descriptions.
Receive and Transmit operations are stopped during RESET. However,
the contents of the transmit and receive data registers (TDR and RDR) are
not changed by RESET.
ASCI Clock
When in external clock input mode, the external clock is directly input to
the sampling rate (÷ 16/÷ 64) as depicted in Figure 56.
Internal Clock
Phi
Baud Rate Selection Prescaler
÷ 1 to ÷ 64
÷ 10 ÷ 30
Sampling Rate
÷ 16 ÷ 64
External Clock
fc ≤ Phi ÷ 40
Figure 56. ASCI Clock
UM005001-ZMP0400