Z80180 Datasheet, PDF (115/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
100
Table 14. Transfer Mode Combinations
DM1 DM0 SM1 SM0 Transfer Mode
1 1 0 0 Memory to I/O
1 1 0 1 Memory to I/O
1 1 1 0 Reserved
1 1 1 1 Reserved
Note: *: includes memory mapped I/O.
Increment/Decrement
SAR0+1, DAR0 fixed
SAR0-1, DAR0 fixed
DMA/WAIT Control Register (DCNTL)
DCNTL controls the insertion of Wait States into DMAC (and CPU)
accesses of memory or I/O Also, the DMA request mode for each DREQ
DREQ0 and DREQ1) input is defined as level or edge sense. DCNTL
also sets the DMA transfer mode for channel 1, which is limited to
memory to/from I/O transfers.
UM005001-ZMP0400