Z80180 Datasheet, PDF (290/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z8018x Family
MPU User Manual
274
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Instruction
Machine
Cycle States Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
T1T2T3 1st Op Code 1st Op
Address
Code
010
1
0*5 1
0
1
MC2
T1T2T3 2nd Op Code 2nd Op
Address
Code
010
1
0*5 1
1
1
MC3
~MC5
TiTiTi *
Z
111
1
1*5 1
1
1
RETI (Z)
MC6
MC7
T1T2T3 1st Op Code
Address
Ti
*
1st Op
Code
Z
010
111
1
0*5 1
1
0
1
1*5 1
1
1
MC8
T1T2T3 2nd Op Code 2nd Op
Address
Code
010
1
0*5 1
1
0
MC9 T1T2T3 SP
data
010
1
1*5 1
1
1
MC10 T1T2T3 SP+1
data
010
1
1*5 1
1
1
RLCA
RLA
RRCA
RRA
MC1
T1T2T3 1st Op Code 1st Op
Address
Code
010
1
01
0
RLC g
RL g
MC1
T1T2T3 1st Op Code 1st Op
Address
Code
010
1
01
0
RRC g
RR g
SLA g
SRA g
SRL g
MC2
MC3
T1T2T3 2nd Op Code 2nd Op
Address
Code
Ti
*
Z
010
111
1
01
1
1
11
1
*5 The upper and lower data show the state of M1 when IOC = 1 and IOC = 0 respectively.
UM005001-ZMP0400