Z80180 Datasheet, PDF (87/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
72
Phi
A0–A19
D0–D7
MI
MREQ
RD
WR
3rd Op Code
Memory
Fetch Cycle Read Cycle
PC stacking
Restart from 0000H
Op Code
fetch cycle
T1 T2 T3 T1 T2 TTP T3 T1 Ti Ti Ti T1 T2 T3 T1 T2 T3 T1 T2 T3
PC
Undefined
Op Code
IX+d, IY+d
SP-1
PCH
SP-2
PCL
0000H
Figure 33. TRAP Timing - 3rd Op Code Undefined
External Interrupts
The Z8X180 features four external hardware interrupt inputs:
• NMI–Non-maskable interrupt
• INT0–Maskable Interrupt Level 0
• INT1–Maskable Interrupt Level 1
• INT2–Maskable Interrupt Level 2
NMI, INT1, and INT2 feature fixed interrupt response modes. INT0 has 3
different software programmable interrupt response modes— Mode 0,
Mode 1 and Mode 2.
NMI - Non-Maskable Interrupt
The NMI interrupt input is edge-sensitive and cannot be masked by
software. When NMI is detected, the Z8X180 operates as follows:
UM005001-ZMP0400