Z80180 Datasheet, PDF (65/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
50
Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) (Continued)
Address
Register
Mnemonic Binary
Hex
DMA DMA Source Address Register Ch 0L SAR0L
XX100000 20H
DMA Source Address Register Ch 0H SAR0H
XX100001 21H
DMA Source Address Register Ch 0B SAR0B
XX100010 22H
DMA Destination Address Register Ch DAR0L
0L
XX100011 23H
DMA Destination Address Register Ch DAR0H
0H
XX100100 24H
DMA Destination Address Register Ch DAR0B
0B
XX100101 25H
DMA Byte Count Register Ch 0L
DMA Byte Count Register Ch 0H
BCR0L
BCR0H
XX100110 26H
XX100111 27H
DMA Memory Address Register Ch 1L MAR1L
XX101000 28H
DMA Memory Address Register Ch 1H MAR1H
XX101001 29H
DMA Memory Address Register Ch 1B MAR1B
XX101010 2AH
DMA I/O Address Register Ch 1L
IAR1L
XX101011 2BH
DMA I/O Address Register Ch 1H
IAR1H
XX101100 2CH
DMA I/O Address Register Ch 1
IAR1B
XX101101 2DH
DMA Byte Count Register Ch 1L
BCR1L
XX101110 2EH
DMA Byte Count Register Ch 1H
BCR1H
XX101111 2FH
DMA Status Register
DSTAT
XX110000 30H
DMA Mode Register
DMODE
XX110001 31H
DMA/WAIT Control Register
DCNTL
XX110010 32H
Page
93
93
93
94
94
94
94
94
94
94
94
102
102
94
94
94
95
97
101
UM005001-ZMP0400