Z80180 Datasheet, PDF (123/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
108
rising edge of the clock prior to T3 at which time the DMA operation
(re)starts. Figure 48 depicts the edge-sense DMA timing.
Phi
DREQ0
DMA
Write
Cycle
CPU
Machine
Cycle
DMA
Read
Cycle
DMA
Write
Cycle
CPU
Machine
Cycle
Tw T3 T1 T2 T3 T1 T2 T3 T1 T2 Tw T3 T1 T2 T3
**
**
**
**
** DREQ0 is sampled at
Figure 48. CPU Operation and DMA Operation DREQ0 is Programmed
for Edge-Sense
During the transfers for channel 0, the TEND0 output goes Low
synchronous with the write cycle of the last (BCR0 = OOH) DMA transfer
(Reference Figure 49).
Last DMA cycle (BCR0 = 00H)
DMA read cycle
DMA write cycle
T1
T2
T3
T1
T2
TW
T3
Phi
TEND0
Figure 49. TEND0 Output Timing Diagram
The DREQ0 and TEND0 pins are programmably multiplexed with the
CKA0 and CKA1 ASCI clock input/outputs. However, when DMA
channel 0 is programmed for memory to/from I/O (and memory to/from
UM005001-ZMP0400