Z80180 Datasheet, PDF (38/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
23
T1
Phi
I/O Read Cycle
T2
TW
T3
I/O Write Cycle
T1
T2
TW
T3
A0–A19
D0–D7
WAIT
IORQ
I/O address
Read data
I/O address
Write data
RD
WR
Figure 13. I/O Read/Write Timing Diagram
Basic Instruction Timing
An instruction may consist of a number of machine cycles including Op
Code fetch, operand fetch, and data read/write cycles. An instruction may
also include cycles for internal processes which make the bus IDLE. The
example in Figure 14 illustrates the bus timing for the data transfer
instruction LD (IX+d),g.
UM005001-ZMP0400